L&T Technology Services Design and Validation Engineer (FPGA) in Iowa
Requirements capture, ASIC/FPGA digital architecture and design using RTL, timing analysis and closure, verification, and system integration.
RTL coding and simulation in VHDL or Verilog
Testbench development for the verification of RTL blocks using VHDL or SystemVerilo
Skills and Abilities required for the Job
RTL coding and simulation in VHDL or Verilog or Testbench development for the verification of RTL blocks using VHDL or SystemVerilog
Digital circuit architecture, design, resource tradeoff, timing analysis and timing closure
Proficiency using ASIC and/or FPGA simulation and sysnthesis tools (e.g. Questasim, Synplify, FPGA-specific tools)
Familiarity with revision control concepts and tools (e.g. clearcase, Subeversion)
Ability to work with minimal supervision, part of a team of engineers with a variety of skills and backgrounds, matrixed into projects with aggressive schedules and frequent milestones.
Strong oral and written communication skills and the ability to document and present one's work and status.
Ability to obtain a Security Clearance, US Citizenship is required
Bachelors Degree in applicable engineering field
Familiarity with best practice chip-level verification techniques and languages
ASIC/FPGA lab validation with advanced lab equipment
Design for test (DFT) and manufacturing issues (optional)
Experienced with Unix, scripting, C/C++, and/or Perl
Bachelor’s Degree in Engineering
Req. Code: 2020-14870
External Company Name: L&T Technology Services
External Company URL: www.lnttechservices.com