Facebook Design for Test (DFT) Engineer Intern in Des Moines, Iowa
Facebook's mission is to give people the power to build community and bring the world closer together. Through our family of apps and services, we're building a different kind of company that connects billions of people around the world, gives them ways to share what matters most to them, and helps bring people closer together. Whether we're creating new products or helping a small business expand its reach, people at Facebook are builders at heart. Our global teams are constantly iterating, solving problems, and working together to empower people around the world to build community and connect in meaningful ways. Together, we can help people build stronger communities - we're just getting started.
Facebook Reality Labs focuses on delivering Facebook's vision through Augmented Reality (AR). Compute power requirements of Augmented Reality require custom silicon. Facebook Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistor, through architecture, to firmware, and algorithms.
Develop and automate DFT flows
Perform DFT rule checks using commercial DFT tools and work with designers to resolve issues
Develop simulation testbenches to verify DFT implementation
Review IP specifications to establish required DFT features
Currently has, or is in the process of obtaining, a Bachelors or Masters in Electrical and Computer Engineering, or related field
Must obtain work authorization in country of employment at the time of hire, and maintain ongoing work authorization during employment
Knowledge of digital design fundamentals and computer architecture
Experience with Python, Perl, TCL or equivalent shell scripting language
Familiarity with SoC/ASIC design flow
Intent to return to degree-program after the completion of the internship/co-op
Knowledge of SOC design flow and DFT practices is a plus, e.g., At-Speed Test, Built-in Self-Test (BIST), Automated Test Pattern Generation (ATPG)
Experience writing Verilog RTL and developing simulation testbenches
Experience with commercial EDA tools for synthesis, simulation, DFT and ATPG
Knowledge of industry test standards (IEEE1149.1, IEEE1500)
Equal Opportunity: Facebook is proud to be an Equal Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Facebook is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at firstname.lastname@example.org.
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